`timescale 1ns/1ns 
module t_qd;
  reg  [7:0] I;
  wire [6:0] oSEG;
  reg  CLK,CLR_n;

initial
  begin
    I[7:0]=8'd0;
    CLK=1'b0;
    CLR_n=1'b1;
  end
 
  always #5 CLK = ~CLK;
  always@(posedge CLK)
  begin
    I[7:0]= {$random}%256;
  end
  
  qd m1(
  .I(I),
  .CLK.(CLK),
  .CLR_n(CLR_n),
  .oSEG(oSEG));
endmodule

